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24AA128/24LC128/24FC128
128K I2CTM CMOS Serial EEPROM
Device Selection Table
Part Number 24AA128 24LC128 24FC128 Note 1: 2: VCC Range 1.7-5.5V 2.5-5.5V 1.7-5.5V Max. Clock Frequency 400 kHz(1) 400 kHz 1 MHz(2) Temp. Ranges I I, E I * Temperature Ranges: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 24AA128/24LC128/ 24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial Electrically Erasable PROM (EEPROM), capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device also has a page write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 128K boundary. Functional address lines allow up to eight devices on the same bus, for up to 1 Mbit address space. This device is available in the standard 8-pin plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP, MSOP, DFN, TDFN and Chip Scale packages.
100 kHz for VCC < 2.5V. 400 kHz for VCC < 2.5V.
Features:
* Single Supply with Operation down to 1.7V for 24AA128/24FC128 devices, 2.5V for 24LC128 Devices * Low-Power CMOS Technology: - Write current 3 mA, typical - Standby current 100 nA, typical * 2-Wire Serial Interface, I2CTM Compatible * Cascadable up to Eight Devices * Schmitt Trigger Inputs for Noise Suppression * Output Slope Control to Eliminate Ground Bounce * 100 kHz and 400 kHz Clock Compatibility * 1 MHz Clock for FC Versions * Page Write Time 5 ms, typical * Self-Timed Erase/Write Cycle * 64-Byte Page Write Buffer * Hardware Write-Protect * ESD Protection >4000V * More than 1 Million Erase/Write Cycles * Data Retention > 200 years * Factory Programming Available * Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN, MSOP, and Chip Scale Packages * Pb-Free and RoHS Compliant
Block Diagram
A0 A1 A2 WP
HV Generator
I/O Control Logic
Memory Control Logic
XDEC
EEPROM Array Page Latches
I/O
SCL YDEC
SDA VCC VSS
Sense Amp. R/W Control
*24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices.
Package Types
PDIP/SOIC A0 A1 A2 VSS 1 24XX128 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 VSS TSSOP/MSOP1 1 24XX128 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 VSS 1 2 3 4 24XX128 DFN/TDFN 8 VCC 7 WP 6 SCL 5 SDA WP 6 CS (Chip Scale)2 VCC A1 A0 1 4 7 2 5 8 3 A2
SDA SCL VSS
(TOP DOWN VIEW, BALLS NOT VISIBLE)
Note 1: Pins A0 and A1 are no-connects for the MSOP package only. 2: Available in I-temp, "AA" only.
2010 Microchip Technology Inc.
DS21191S-page 1
24AA128/24LC128/24FC128
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
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VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-40C to +125C ESD protection on all pins 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40C to +85C Automotive (E): VCC = +2.5V to 5.5V TA = -40C to 125C Characteristic A0, A1, A2, SCL, SDA and WP pins: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Min. -- 0.7 VCC -- 0.05 VCC -- -- -- -- -- -- Standby current -- Max. -- -- 0.3 VCC 0.2 VCC -- 0.40 1 1 10 400 3 1 Units -- V V V V V A A pF A mA A -- -- VCC 2.5V VCC < 2.5V VCC 2.5V (Note 1) IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC VOUT = VSS or VCC VCC = 5.0V (Note 1) TA = 25C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V TA = -40C to +85C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS TA = -40C to 125C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS Conditions
DC CHARACTERISTICS Param. No. Sym. -- D1 D2 D3 D4 D5 D6 D7 D8 D9 VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICCS
ICC Read Operating current
--
5
A
Note 1: This parameter is periodically sampled and not 100% tested.
DS21191S-page 2
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40C to +85C Automotive (E): VCC = +2.5V to 5.5V TA = -40C to 125C Characteristic Clock frequency Min. -- -- -- -- 4000 600 600 500 4700 1300 1300 500 -- -- -- -- -- 4000 600 600 250 4700 600 600 250 0 250 100 100 4000 600 600 250 4000 600 600 4700 1300 1300 Max. 100 400 400 1000 -- -- -- -- -- -- -- -- 1000 300 300 300 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units kHz Conditions 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 5.5V 24FC128 All except, 24FC128 1.7V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 (Note 2) 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 5.5V 24FC128 1.7 V VCC 2.5V 2.5 V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5 V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 5.5V 24FC128
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AC CHARACTERISTICS Param. No. 1 Sym. FCLK
2
THIGH
Clock high time
ns
3
TLOW
Clock low time
ns
4
TR
SDA and SCL rise time (Note 1) SDA and SCL fall time (Note 1)
ns
5 6
TF
ns ns
THD:STA Start condition hold time
7
TSU:STA
Start condition setup time
ns
8 9
THD:DAT Data input hold time TSU:DAT Data input setup time
ns ns
10
TSU:STO Stop condition setup time
ns
11
TSU:WP
WP setup time
ns
12
THD:WP
WP hold time
ns
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model, which can be obtained from Microchip's web site at www.microchip.com.
2010 Microchip Technology Inc.
DS21191S-page 3
24AA128/24LC128/24FC128
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS Param. No. 13 Sym. TAA Characteristic Output valid from clock (Note 2)
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Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40C to +85C Automotive (E): VCC = +2.5V to 5.5V TA = -40C to 125C Min. -- -- -- -- 4700 1300 1300 500 10 + 0.1CB Max. 3500 900 900 400 -- -- -- -- 250 250 50 5 -- Units ns Conditions 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 All except, 24FC128 (Note 1) 24FC128 (Note 1) All except, 24FC128 (Notes 1 and 3) --
14
TBUF
Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum CB 100 pF Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance
ns
15
TOF
ns
16 17 18
TSP TWC --
-- -- 1,000,000
ns ms
cycles Page Mode, 25C, 5.5V (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model, which can be obtained from Microchip's web site at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5 2 D3 4
SCL SDA IN
7 6 16
3
8
9
10
13 SDA OUT (protected) (unprotected)
14
WP
11
12
DS21191S-page 4
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
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TABLE 2-1:
Name A0 A1 (NC) A2 VSS SDA SCL WP VCC 1 2 -- 3 4 5 6 7 8
PIN FUNCTION TABLE
SOIC 1 2 -- 3 4 5 6 7 8 TSSOP 1 2 -- 3 4 5 6 7 8 MSOP -- -- 1, 2 3 4 5 6 7 8 DFN(1) 1 2 -- 3 4 5 6 7 8 TDFN(1) 1 2 -- 3 4 5 6 7 8 CS 3 2 -- 5 8 6 7 4 1 Function User Configurable Chip Select User Configurable Chip Select Not Connected User Configurable Chip Select Ground Serial Data Serial Clock Write-Protect Input +1.7V to 5.5V (24AA128) +2.5V to 5.5V (24LC128) +1.7V to 5.5V (24FC128)
PDIP
Note 1:
The exposed pad on the DFN/TDFN package can be connected to VSS or left floating.
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX128 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the MSOP package only, pins A0 and A1 are not connected. Up to eight devices (two for the MSOP package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic `0' or logic `1'. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic `0' or logic `1' before normal device operation can proceed.
This input is used to synchronize the data transfer to and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited but read operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.
The 24XX128 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24XX128 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated.
2010 Microchip Technology Inc.
DS21191S-page 5
24AA128/24LC128/24FC128
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1).
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The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.
4.5
Acknowledge
4.1 4.2
Bus Not Busy (A) Start Data Transfer (B)
Both data and clock lines remain high.
Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Note: The 24XX128 does not generate any Acknowledge bits if an internal programming cycle is in progress.
A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX128) will leave the data line high to enable the master to generate the Stop condition.
FIGURE 4-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
Start Condition
Address or Acknowledge Valid
Data Allowed to Change
Stop Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
DS21191S-page 6
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
5.0 DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code. For the 24XX128, this is set as `1010' binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX128 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. For the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figures 5-1 and 5-2) should be set to `0'. Only two 24XX128 MSOP packages can be connected to the same bus. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A13...A0 are used, the upper two address bits are "don't care" bits. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX128 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a `1010' code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX128 will select a read or write operation.
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CONTROL BYTE FORMAT
Read/Write Bit Chip Select Bits 0 A2 A1 A0 R/W ACK
Control Code S 1 0 1
Slave Address Start Bit Acknowledge Bit
5.1
Contiguous Addressing Across Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 1 Mbit by adding up to eight 24XX128 devices on the same bus. In this case, software can use A0 of the control byte as address bit A14; A1 as address bit A15; and A2 as address bit A16. It is not possible to sequentially read across device boundaries. For the MSOP package, up to two 24XX128 devices can be added for up to 256 Kbit of address space. In this case, software can use A2 of the control byte as address bit A16. Bits A0 (A14) and A1 (A15) of the control byte must always be set to logic `0' for the MSOP.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Address High Byte Address Low Byte
Control Byte
1
0
1
0
A 2
A 1 Chip Select Bits
A 0 R/W
x
x
AAAA 13 12 11 10
A 9
A 8
A 7
*
*
*
*
*
*
A 0
Control Code
x = "don't care" bit
2010 Microchip Technology Inc.
DS21191S-page 7
24AA128/24LC128/24FC128
6.0
6.1
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WRITE OPERATIONS
Byte Write
6.3
Write Protection
Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX128. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX128, the master device will transmit the data word to be written into the addressed memory location. The 24XX128 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX128 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. Note: When doing a write of less than 64 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page.
The WP pin allows the user to write-protect the entire array (0000-3FFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
6.2
Page Write
The write control byte, word address, and the first data byte are transmitted to the 24XX128 in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the six lower Address Pointer bits are internally incremented by `1'. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command.
DS21191S-page 8
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
FIGURE 6-1:
Bus Activity Master SDA Line Bus Activity
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BYTE WRITE
S T A R T
Control Byte
Address High Byte
xx A C K A C K
Address Low Byte
Data
S T O P P
S 1 0 1 0AAA 0 210
A C K
A C K
x = "don't care" bit
FIGURE 6-2:
Bus Activity Master SDA Line Bus Activity
PAGE WRITE
S T A R T
Control Byte
Address High Byte
xx A C K A C K
Address Low Byte
Data Byte 0
Data Byte 63
S T O P P A C K
AAA S10102 100
A C K
A C K
x = "don't care" bit
7.0
ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram.
ACKNOWLEDGE POLLING FLOW
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? Yes Next Operation
No
2010 Microchip Technology Inc.
DS21191S-page 9
24AA128/24LC128/24FC128
8.0 READ OPERATION
8.2 Random Read
Read operations are initiated in much the same way as write operations with the exception that the R/W bit of the control byte is set to `1'. There are three basic types of read operations: current address read, random read and sequential read.
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8.1
Current Address Read
The 24XX128 contains an address counter that maintains the address of the last word accessed, internally incremented by `1'. Therefore, if the previous read access was to address `n' (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to `1', the 24XX128 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX128 discontinues transmission (Figure 8-1).
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX128 as part of a write operation (R/W bit set to `0'). Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a `1'. The 24XX128 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition, which causes the 24XX128 to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read.
8.3
Sequential Read
FIGURE 8-1:
S T A R T
CURRENT ADDRESS READ
Control Byte Data Byte
S T O P P A C K N O A C K
Bus Activity Master SDA Line Bus Activity
S 10 10 AAA1 210
Sequential reads are initiated in the same way as a random read except that after the 24XX128 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX128 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a Stop condition. To provide sequential reads, the 24XX128 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 3FFF to address 0000 if the master acknowledges the byte received from the array address 3FFF.
S T A R T A C K
FIGURE 8-2:
Bus Activity Master
RANDOM READ
S T A R T
Control Byte Address High Byte Address Low Byte Control Byte Data Byte
S T O P P N O A C K
SDA Line Bus Activity
S1 01 0 AAA0 210 A C K
xx A C K
S 1 0 1 0 A A A1 210
A C K
x = "don't care" bit
FIGURE 8-3:
Bus Activity Master SDA Line Bus Activity
SEQUENTIAL READ
Control Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x) S T O P P A C K A C K A C K A C K N O A C K
DS21191S-page 10
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
9.0
9.1
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PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW Example: 24AA128 I/P e3 017 0510
8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN
Example: 24LC128I SN e3 0510 017
8-Lead SOIC (5.28 mm) XXXXXXXX T/XXXXXX YYWWNNN
Example: 24LC128 I/SM e3 0510017
8-Lead TSSOP XXXX TYWW NNN
Example: 4LC I510 017
8-Lead Chip Scale XXXXXXX YYWWNNN
Example: 24AA128 0810017
2010 Microchip Technology Inc.
DS21191S-page 11
24AA128/24LC128/24FC128
Package Marking Information (Continued)
8-Lead MSOP XXXXXT YWWNNN Example: 4L128I 051017
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8-Lead DFN-S
Example:
XXXXXXX T/XXXXX YYWW NNN
24LC128 I/MF 0510 017
8-Lead 2x3 TDFN
XXX YWW NN
Example:
A84 510 I7
First Line Marking Codes Part Number 24AA128 24LC128 24FC128 Legend: XX...X T Y YY WW NNN TSSOP 4AC 4LC 4FC MSOP I-Temp 4A128T 4L128T 4F128T A81 A84 A8A TDFN E-Temp -- A85 --
e3
Note:
Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn)
For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
Note:
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21191S-page 12
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
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2010 Microchip Technology Inc.
DS21191S-page 15
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DS21191S-page 16
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
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For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
DS21191S-page 17
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DS21191S-page 18
2010 Microchip Technology Inc.
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DS21191S-page 19
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DS21191S-page 20
2010 Microchip Technology Inc.
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DS21191S-page 21
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DS21191S-page 22
2010 Microchip Technology Inc.
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DS21191S-page 24
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
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2010 Microchip Technology Inc.
DS21191S-page 25
24AA128/24LC128/24FC128
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DS21191S-page 26
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
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DS21191S-page 27
24AA128/24LC128/24FC128
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For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS21191S-page 28
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
DS21191S-page 29
24AA128/24LC128/24FC128
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS21191S-page 30
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
APPENDIX A:
Revision L
Corrections to Section 1.0, Electrical Characteristics.
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REVISION HISTORY
Revision M
Added 1.8V 400 kHz option for 24FC128.
Revision N
Revised Sections 2.1, 2.4 and 6.3. Removed 14-Lead TSSOP Package.
Revision P
Changed 1.8V to 1.7V throughout document; Revised Features Section; Replaced Package Drawings; Revised Product ID Section.
Revision Q (June 2008)
Updated packaging; Added Chip Scale package.
Revision R (04/2009)
Updated Chip Scale package.
Revision S (05/2010)
Added TDFN Package; Updated Package Drawings and Product ID.
2010 Microchip Technology Inc.
DS21191S-page 31
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NOTES:
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2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
www..com
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
2010 Microchip Technology Inc.
DS21191S-page 33
24AA128/24LC128/24FC128
READER RESPONSE
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It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21191S FAX: (______) _________ - _________
Device: 24AA128/24LC128/24FC128 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21191S-page 34
2010 Microchip Technology Inc.
24AA128/24LC128/24FC128
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package
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Examples: a) b) 24AA128-I/P: Industrial Temp., 1.7V, PDIP package. 24AA128T-I/SN: Tape and Reel, Industrial Temp., 1.7V, SOIC package. 24AA128-I/ST: Industrial Temp., 1.7V, TSSOP package. 24AA128-I/MS: Industrial Temp., 1.7V, MSOP package. 24AA128T-I/CS15K:Industrial Temp., 1.7V, CS package, Tape and Reel 24LC128-E/P: Extended Temp., 2.5V, PDIP package. 24LC128-I/SN: Industrial Temp., 2.5V, SOIC package. 24LC128T-I/SN: Tape and Reel, Industrial Temp., 2.5V, SOIC package. 24LC128-I/MS: Industrial Temp., 2.5V, MSOP package. 24LC128T-I/MNY: Tape and Reel, Industrial Temp., 2.5V, TDFN package. 24FC128-I/P: Industrial Temp., 1.7V, High Speed, PDIP package. 24FC128-I/SN: Industrial Temp., 1.7V, High Speed, SOIC package.
Device:
24AA128: 24AA128T: 24LC128: 24LC128T: 24FC128: 24FC128T:
128 Kbit 1.7V I2C Serial EEPROM 128 Kbit 1.7V I2C Serial EEPROM (Tape and Reel) 128 Kbit 2.5V I2C Serial EEPROM 128 Kbit 2.5V I2C Serial EEPROM (Tape and Reel) 128 Kbit High Speed I2C Serial EEPROM 128 Kbit High Speed I2C Serial EEPROM (Tape and Reel) -40C to +85C -40C to +125C
c) d) e)
f) g) h)
Temperature Range: Package:
I E P SN
= =
= Plastic DIP (300 mil body), 8-lead = Plastic SOIC (3.90 mm body), 8-lead SM = Plastic SOIC (5.28 mm body), 8-lead ST = Plastic TSSOP (4.4 mm), 8-lead MF = Dual, Flat, No Lead (DFN-S) (6x5 mm body), 8-lead MNY(1) = TDFN (2x3x0.75 mm body), 8-lead MS = Plastic Micro Small Outline (MSOP), 8-lead CS15K(2) = Chip Scale (CS), 8-lead (I-temp, "AA", Tape and Reel only)
i) j)
k) l)
Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish. 2: "15K" indicates 150K technology
m) 24FC128T-I/SN: Tape and Reel, Industrial Temp., 1.7V, High Speed, SOIC package
2010 Microchip Technology Inc.
DS21191S-page35
24AA128/24LC128/24FC128
NOTES:
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DS21191S-page36
2010 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-167-3
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc.
DS21191S-page 37
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS21191S-page 38
2010 Microchip Technology Inc.

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